Reconfigurable compute engines in the past have been connected together so as to provide a computational system which can address many different types of tasks utilizing the same computer elements. Reconfigurable compute engines in general are exemplified by the field programmable gate arrays which when interconnected and appropriately programmed provide such functions as communications, signal intelligence, spatial processing, and jamming. When a suite of electronics is provided in an aircraft, it is oftentimes desirable to be able to reutilize the compute engines by changing their modes on the fly so that the avionics suite performs the above noted functions.
The reason for the utilization of field programmable gate arrays is so that the amount of equipment in an aircraft payload can be minimized due to space and power limitations. However, present field programmable gate arrays, FPGAs, are at present only programmable by programming the entire unit, and thus regardless of the different applications instantiated in the FPGAs oftentimes all interconnects must be changed to effectuate each mode change.
Inherent in the programming of such FPGAs is the ability to configure a physical layer which is coupled to the application programmed into the FPGA so as to provide input and output pins which carry data, timing, and other signals between the FPGAs that are connected together to provide a particular function.
Thus, it is important that the interconnect between the FPGAs support, inter alia, low deterministic latencies on the order of 1 to 10 nanoseconds and support edge sensitive signal distribution, for instance, for clocks, strobes, triggers and the like. There is also a need for the physical layer to support synchronized data transport.
In general, in order to provide the programming for a system composed of a number of FPGAs, it usually takes 400 man-hours to generate an FPGA configuration, which is preceded by research and development typically on the order of another 400 man-hours. Thus, for each mode of operation of the FPGAs, upwards of 800 man-hours are required.
Were one wishing to change the mode of operation of the FPGAs in an electronics bay of an aircraft one would not want to completely reprogram each one of the FPGAs for each mode of operation, nor rewire the interconnects between the modules. Thus when changing the mode from communications to, for instance, spatial processing, since there is a suite of software which is capable of supporting both applications without alteration, it would be highly desirable to be able to provide a reconfigurable fabric which could selectively connect each of the FPGA modules together and support, for instance, all of the timing required, including strobing, clock triggers and the like, and to, for instance, simultaneously accommodate packet switched networks as well as circuit switched networks. Moreover, whatever interconnect fabric is supplied, it must be as flexible and scalable as possible so as to utilize the various resources and switch between them on demand.
There exist systems where the functionality resides in either general purpose processors, GPPs, or reconfigurable compute engines, RCE, or combinations thereof. Such systems require interconnect fabrics that support a wide range of data flow. While general purpose processors have interconnect requirements that are being satisfied by current technologies such as Ethernet and Myrinnet, there is no suitable fabric with characteristics appropriate for use between reconfigurable compute engines.
Nowhere is such an interconnect fabric more urgently needed than in command, control, communications and computers used for intelligence, surveillance and reconnaissance. In some initiatives one needs to have a single system that can support communications, signal intelligence, jamming and run on the same hardware. As an example, it is an important requirement to have the hardware configured to have a number of receive channels and a number of transmit channels and to reconfigure the RCEs either to perform a communications function, signal intelligence or jamming.
As mentioned above, the RCEs presently are realized using FPGAs, with the combination of the FPGAs, for instance, in communications having a tuner that feeds them, with the FPGAs then feeding some processor and feeding back up to another FPGA and then to a transmitter. The interconnection protocols for connecting the FPGAs together provide for the receive and the transmit functions associated with communications.
On the other hand signal intelligence systems have only a tuner, FPGA and a processor. It will be appreciated that when operated in this mode there is no transmission so that only one half of the system normally configured for communications need be used. A jammer usually has processing followed by a FPGA, with the output of the FPGA then coupled to a transmitter so that the jammer consists in essence of a receiver and processing, with the output utilized to drive a transmitter for counter measure purposes.
In any avionics suite, there may be up to a dozen FPGAs which are connected to do many of a variety of functions. For instance at any given time, one might utilize five FPGAs to do communications and two to do signal intelligence. Later one might want to change the avionics around so that other FPGAs are connected together to provide, for instance, a spatial processing task or a jamming function.
In the past, one would utilize a well-defined static interconnection system for whatever mode or function was required to enable one FPGA to talk with another one.
However, because multi-mission systems are desired, it is important to be able to make the avionics package completely reconfigurable so that any FPGA can communicate with any other FPGA. In order to do so one needs a data fabric to allow the FPGAs to exchange data at high rates with low and deterministic latencies.
In order to connect the FPGAs, at the physical layer, one is talking about the ability to sustain a certain bandwidth on a given twisted pair. For twisted pairs one considers point-to-point terminations and the twisted pairs should be able to accommodate an edge sensitive strobe. It should be able to accommodate packet switched data, circuit switched data, or to accommodate fixed point-to-point connections with synchronized or asynchronized data.
Beyond the physical layer, one needs to be able to provide for different protocol stacks. Depending on the function implemented in any one of the reconfigurable compute engines, the particular protocol stack determines the kind of signaling whether it be discrete strobes, packet switched or circuit switched type of topologies or the like which have to be supported.
In short, one needs to have a common suite of hardware that would perform the multi-mission or multi-mode architecture. One therefore needs a fabric that has the ability to support all the different interconnect methods without having to go and change the underlying hardware.
Not only must the interconnect fabric support all kinds of clocks, it must also support those whose clock rates require that there be some minimum number of clock edges. It must also accommodate 8 B/10 B encoded signals and for instance, must support 10 MHz square wave clock pulses. The fabric must also be able to support discrete signals or signals which involve a simple level which is changed.
While the above lists some of the types of signals that one could expect, one also needs to have the fabric support a number of different mode changes without having to reload the FPGA. In short, one could think of the fabric that needs to be provided as a distributed switch architecture where the intelligence lies in each reconfigurable compute node.
In short, the fabric or physical structure should be able to support two modes. One mode is one in which there are parameters that are set as bits in a register or are embedded in each reconfigurable compute engine that defines what pins are to exist at one FPGA node. The pins are arranged such that they are either source pins, destination pins or pass through pins. However, just supporting the above while supporting a limited number of reconfiguration states is insufficient. What is required is a structure that does not lend itself to just being a bit in a register. What is necessary is the reloading of some number of the FPGAs so that complimentary configurations can be instantiated so that several of the FPGAs can talk to each other.
In short, what is necessary is logic that is installed in the FPGAs to instruct the way that the FPGAs are interconnected and allows one to change the way they are interconnected without having to reload the FPGA or without having to rewire them. What is therefore necessary is to have some modality to a virtual circuits set up that can be torn down at any time that a mode change needs to be made. With the respect to the pins for the FPGAs, a pin on a node needs to be able to be configured to be a transmitter, a receiver or beyond that to function as a pair for differential signal arrangements that can accommodate edge sensitive reconfigurable strobes or encoded signal structures. A reconfigurable fabric also needs to be able to accommodate either packet switched topologies or circuit switched topologies or combinations of each, as well as accommodating singleton kinds of implementations. Moreover, the fabric needs to be able to accommodate optical translations.